| 1. Class 08:00h - 08:45h | 2. Class 08:50h - 09:35h | 3. Class 09:45h - 10:30h | 4. Class 10:35h - 11:20h | 5. Class 11:30h - 12:15h | 6. Class 12:20h - 13:05h | 7. Class 13:10h - 13:55h | 8. Class 14:00h - 14:45h | 9. Class 14:50h - 15:35h | 10. Class 15:45h - 16:30h | 11. Class 16:35h - 17:20h | 12. Class 17:25h - 18:10h | 13. Class 18:15h - 19:00h | 14. Class 19:10h - 19:55h | 15. Class 20:00h - 20:45h | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Modnay
|
FPGA programming (P)
Bojan Kuljić
Room 303
|
FPGA programming (LV)
Bojan Kuljić
Room 303
|
Designing embedded systems (P)
Peter Odri
Room 407A
|
Designing embedded systems (LV)
Peter Odri
Room 407A
|
|||||||||||
|
Tuesday
|
Animation (LV)
Tibor Sakal
Room 301
|
Microcontrollers (P)
Mikloš Pot
Room 301
|
Project - electrical engineering (AV)
Sanja Maravić Čisar
Room 1
|
||||||||||||
|
Wednesday
|
Animation (P)
Tibor Sakal
Room A2
|
Microcontrollers (LV)
Mikloš Pot
Room 303
|
|||||||||||||
|
Thursday
|
|||||||||||||||
|
Friday
|
German language (P)
Karmelka Barić
Room A1
|
German language (AV)
Karmelka Barić
Room A1
|
Company Organization (AV)
Igor Fürstner
Room A0
|
Company Organization (P)
Igor Fürstner
Room 106
|
|||||||||||